When the clock frequency exceeds 5MHz, or the signal rise time is less than 5ns, in order to control the signal loop area well, it is generally necessary to use a multi-layer board design (high-speed PCBs are generally designed with multi-layer boards). When designing multilayer boards, we should pay attention to the following principles:
1. The key wiring layer (the layer where clock lines, buses, interface signal lines, radio frequency lines, reset signal lines, chip select signal lines, and various control signal lines are located) should be adjacent to the complete ground plane, preferably between the two ground planes. Key signal lines are generally strong radiation or extremely sensitive signal lines. Wiring close to the ground plane can reduce the signal loop area, reduce its radiation intensity or improve anti-interference ability.
2. The power plane should be retracted relative to its adjacent ground plane (recommended value 5H～20H). The retraction of the power plane relative to its return ground plane can effectively suppress the "edge radiation" problem. In addition, the main working power plane of the board (the most widely used power plane) should be close to its ground plane to effectively reduce the loop area of the power supply current.
3. Whether there is no signal line ≥50MHz on the TOP and BOTTOM layers of the board. If so, it is best to walk the high-frequency signal between the two plane layers to suppress its radiation to the space. The number of layers of a multi-layer board depends on the complexity of the circuit board. The number of layers and stacking scheme of a PCB design depends on the hardware cost, the wiring of high-density components, signal quality control, schematic signal definition, and PCB manufacturer's processing capability baseline And other factors.
